1. Field
Various embodiments of the present disclosure relate to a level shifter and a parallel-to-serial converter including the same.
2. Description of the Related Art
Many electronic circuits having various functions may be integrated in a single integrated circuit. Often, the various electronic circuits may operate at different voltages, in which case, an interface circuit may be required to shift the voltage levels of signals transmitted between the circuits. Such an interface circuit is generally referred to as a level shifter circuit or a level shifter.
FIG. 1 is a circuit diagram illustrating a conventional level shifter.
Referring to FIG. 1, a conventional level shifter may be configured to receive signals that may vary between a ground voltage level and a first power source voltage level VDD1 through an input terminal IN and a complementary input terminal INB, to generate signals that may vary between the ground voltage level and VDD2 (a second power source voltage having a level higher than that of VDD1) level, and to output the generated signals to an output terminal OUT and a complementary output terminal OUTB.
In a conventional level shifter, an error may be generated when the input signals to the input terminals IN and INB are transient.
For example, when a signal inputted to the input terminal IN is transitioning from a ground voltage level to a VDD1 level, a fighting may occur between the P-type metal-oxide-semiconductor (PMOS) transistor 101, which is already turned on, and the N-type metal-oxide-semiconductor (NMOS) transistor 103. If the NMOS transistor 103 may be sufficiently turned on, the voltage level of the complementary output terminal OUTB may be decreased, while a voltage level of the output terminal OUT may be increased, causing the PMOS transistor 102 to turn on and the PMOS transistor 101 to turn off, so that eventually the fighting between the PMOS transistor 101 and the NMOS transistor 103 may be settled. However, when the difference of the voltage levels of VDD1 and VDD2 is large, the NMOS transistor 103 may not be turned on sufficiently, generating an error wherein the fighting phenomenon between the two transistors may continue for a substantial amount of time negatively impacting the operation of the level shifter.